The MTL (Merge Transistor Logic) technology also known as I.sup.2 L (Integrated Injection Logic) is well known in the art. The history of this technology and the most important publications concerning this subject, can be found in French Patent Application No. 77/29867 filed on Sept. 28, 1977 by the applicant of the present invention, and published under U.S. Pat. No. 2,404,962. French Patent Application No. 77/29867--U.S. patent application Ser. No. 924,126 filed July 13, 1978 entitled "Semiconductor Integrated Injection Logic Structure Controlled by the Injector" by R. H. Hornung et al. and granted on July 7, 1981 as U.S. Pat. No. 4,277,701. The above indicated French patent shows how it is possible to obtain different response times by varying as required the spacing between the injection rail and the base of the various NPN transistors, and thus, to provide the injection with a logic control function, in particular for prepositioning flip-flops into a predetermined logic state when applying power.
Further, this technology (MTL or I.sup.2 L) and its various applications has been described in a number of U.S. Patents and Publications, a number of which are identified below:
U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1974 to S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,886,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A Semiconductor Memory System" granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith.
IBM Technical Disclosure Bulletin publication entitled "I.sup.2 L/MTL Storage Cell Layout" by H. H. Berger et al., Vol. 22, No. 10, March 1980, pages 4604-5.
IBM Technical Disclosure Bulletin publication entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1, June 1978, pages 231-2.
"Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 340-6.
"Integrated Injection Logic: A New Approach to LSI" by Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 346-51.
"I.sup.2 L Takes Bipolar Integration A Significant Step Forward" by R. L. Horton et al., Electronics, Feb. 6, 1975, pages 83-90.
"I.sup.2 L Puts It All Together For 10-bit a-d Converter Chip" by Paul Brokaw, Electronics/Apr. 13, 1978, pages 99-105.
"Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 6, Mar. 15, 1974, pages 28 and 30.